ChipStart ASIC Design
World-Class Semiconductor IP Without Starting from Scratch.
Designing a custom ASIC or integrating semiconductor IP shouldn't mean months of ramp-up, hand-rolled infrastructure, and reinventing the wheel. ChipStart® ASIC Design gives semiconductor, consumer electronics, and IoT companies access to proven analog and digital IP blocks, expert integration services, and a deep partner ecosystem so you can move faster, reduce risk, and put your engineering resources where they matter most.
Custom Silicon Is Hard.
The Right IP Partner Makes It Manageable.
Every ASIC design project starts with a familiar tension: the pressure to ship on time, the complexity of integrating reliable IP, and the risk of choosing the wrong building blocks at the wrong stage of development.
Building analog and digital IP in-house is expensive, time-consuming, and often extraneous to your core differentiation. Sourcing from fragmented vendors adds integration risk and support uncertainty. And navigating the ASIC ecosystem, from design and testing tools to foundry relationships to EDA partnerships, requires experience most lean engineering teams don't have the bandwidth to develop.
ChipStart was built for exactly this problem. We bring proven IP, deep integration expertise, and a trusted partner network to your design program so your team can focus on the innovation that actually wins in the market.
The ChipStart Advantage
Choosing the right semiconductor IP and integration partner isn't just a technical decision. It's a business decision that shapes your schedule, risk profile, and competitive position. ChipStart is built around four principles that translate directly into better outcomes for your design program.
It starts with performance you can rely on and extends to the ability to embed the latest functional advances without having to start over. We deliver the economics that keep your program viable with IP that's structured to protect and amplify your investment.
Performance Efficiency – Our analog and digital IP blocks are engineered for efficiency and validated across process nodes and design environments. They deliver the timing, area, and power characteristics your architecture requires, optimized for your configurations, rather than inherited from other designs' constraints.
Functional Advancements – The semiconductor landscape evolves rapidly with new processes, technologies, and interface standards. Our portfolio of current-generation IP is designed to adapt to your product roadmap evolution, keeping pace with functional demands while eliminating expensive re-architecture every product cycle.
Cost Optimization – Building IP from scratch is expensive and time-consuming. Fragmented IP from multiple vendors increases integration costs and support risk. We consolidate proven IP, expertise, and ecosystem partnerships into one engagement that optimizes cost, compresses schedules, and delivers faster tapeouts with fewer surprises.
Design & IP Selection – Architecture-stage decisions determine design economics. We bring integration expertise and deep IP portfolio to early-program stages, helping your team make smart build/buy/license trade-offs before they're costly to change. We optimize existing IP portfolios for maximum reuse and minimal redundancy.
Together, these advantages mean you're not just getting an IP design partner. You're tapping into a wealth of knowledge and experience that can help you optimize your operations and resources to deliver a better product that drives business growth.
Trusted Partner Network
Great ASIC design doesn't happen in a vacuum. It depends on the right EDA tools, the right foundry relationships, and partners who have worked together long enough to know where the integration bodies are buried.
ChipStart has spent years building and maintaining relationships across the semiconductor design ecosystem, from EDA vendors and IP libraries to foundry partners and reference design programs.
When you work with ChipStart, you inherit that network.
Design Tool Ecosystem – Our IP and integration services are validated against industry-standard EDA platforms, ensuring that the IP you license or integrate doesn't create toolchain friction in your existing design environment.
Foundry & Process Relationships – Our team has direct experience working across leading process nodes and foundry environments to reduce the risk of process-level surprises late in the design cycle.
Industry Partner Program – We maintain active relationships with complementary IP vendors, design services firms, and semiconductor industry organizations, giving clients access to an expanded ecosystem to support a robust design program.
Semiconductor IP and Integration Services
ChipStart ASIC Design empowers clients to accelerate innovation and efficiency. Our services are integral to a wide range of consumer and industrial technologies, delivered across the following core service capabilities:
Semiconductor IP Design
Custom ASIC design for semiconductor chips, covering FPGA, ASIC, and related design work from initial architecture all the way through tape-out and final production.
IP Integration
End-to-end IP integration consulting and delivery, from architecture review through tape-out support. ChipStart works alongside your engineering team to manage the complexity of integrating third-party and proprietary IP blocks.
IP Aggregation & Licensing
IP portfolio aggregation and licensing program management for companies looking to structure and commercialize their IP assets.
Packaging Services
ChipStart offers a full suite of assembly services for semiconductor packaging, including leadframe, laminate, flip-chip interconnect, and advanced wafer-level technology.
We differentiate ourselves with a comprehensive wafer-level platform, including Fan-in and Fan-out WLP, Integrated Passive Devices, and Through Silicon Via. These services were built for next-generation devices demanding higher integration, functionality, and compact size. We work closely with customers on die and package design to deliver the best performance, quality, cycle time and cost.
We support the following package technologies:
- Flip Chip Packages
- System-in-Package (SiP)
- Wafer Level Packages (WLP)
- Wirebond Packages
SoC System Management Service (SSM)
Centralized system management architecture for complex SoCs that provides integrated hardware IP and software for power management, security, boot control, error handling, system monitoring, and platform management functions.
Lower design and verification risks by simplifying system management architecture
- Improve effectiveness by enabling any policy setting source to directly connect and control hardware
- Standardize on one flexible and scalable scheme for all products
- Centralize system management on one IP block with complete system visibility
- Create management transparency with other hardware and software so that hardware and software can be easily interchanged while maintaining the overall management scheme
- Improve system operations by enable new levels of real time management control through context switching policies and enforcement
- Improve error detection and recovery through well coordinated procedures
- Improve security of sensitive differentiable innovations via unique “secure boot” operation
- Lower manufacturing costs for derivatives through JTAG based firmware boot management
Custom Memory Design
Memory configuration, selection, integration, and performance tuning to optimize bandwidth, latency, power consumption, and overall system efficiency.
180nm Low Leakage SRAM
The 180nm Low Leakage SRAM is an 8Kx32 single port static RAM that is designed into TSMC’s 0.18μm CMOS process. It uses the lower four metals (all thin) and can be freely overrouted with higher level interconnects.
The design is optimized for standby power and makes use of standard Vt and high Vt thin oxide MOSFETs plus thick oxide (3.3V) I/O transistors. A deep sleep mode is embodied which shuts down the power to all peripheral circuitry and to selected banks of SRAM cells. In those banks where data is to be retained, the internal power supply connection is maintained and an n-channel source biasing technique is used to reduce leakage current when not being accessed.
The design uses conventional row-column physical decoding and partitions the array vertically into eight banks. A segmented bitline architecture with local column decode
is used to improve speed and reduce active power consumption.
MEMORY COMPILER FEATURES
- BIST (Built-In Self Test) Aware
- Customer may use internal test muxes or external BIST
- Area or Performance Switch
- Customer sets compiler priority switch to compile for optimal speed or size
- Byte Masking
- Subword select option
- Port A/B setup mode (Read/Write) option (for DP SRAM)
- Security and Test Mode for OTP NVM
- Selectable Charge Pump Option for OTP NVM Cell Programming
- Built in internal VPPI source, or
- External source
MEMORY COMPILER CHARACTERISTICS
Data Access: Configurable
Dual Port: Each Port is configurable
Input Latching: Input signals are latched at rising clock edge
BIST: Configurable On/Off
Over Routing: Max 3 metal layers used
CSLLSRAM090_4KX40 & CSLLSRAM090_8KX40 90NM LOW LEAKAGE STATIC RANDOM ACCESS MEMORIES
The CSLLSRAM090 is a x40 single port SRAM in either 4Kword or 8Kword configurations that is designed into TSMC’s CLN90LP CMOS process. It uses the lower four metals (all thin) and can be freely over-routed with higher level interconnects.
The design is optimized for standby power and makes use of both standard Vt and high Vt MOSFETs. A deep sleep mode is embodied which shuts down the power to all
peripheral circuitry and to selected banks of SRAM cells. In those banks where data is to be retained, the internal power supply connection is maintained and an n-channel source biasing technique is used to reduce leakage current when not being accessed.
The design uses conventional row-column physical decoding and partitions the array vertically into four (4KWord) or eight (8KWord) banks. A segmented bitline
architecture with local column decode is used to improve speed and reduce active power consumption.
A synchronous clear function is implemented for the addressed bank, where 128 address locations are cleared
to zero in one clock cycle.
Product Engineering
ChipStart delivers turnkey product engineering solutions from initial prototyping through mass production, backed by a fully integrated supply chain. Our advanced technology design helps customers build their business efficiently, expediting time-to-market and time-to-volume. For Digital Currency, we manage the full lifecycle for our customers. This starts with chip design and chip manufacturing to system design and system manufacturing, spanning hardware, software and cloud services.
Let's Talk About Your Design Program
Whether you're sourcing IP, evaluating integration support, or building out a licensing program – we'd like to hear about what you're working on.